The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
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cve-icon MITRE Information

Status: PUBLISHED

Assigner: XEN

Published: 2024-01-05T16:30:57.225Z

Updated: 2024-01-05T16:30:57.225Z

Reserved: 2023-06-01T10:44:17.065Z


Link: CVE-2023-34326

JSON object: View

cve-icon NVD Information

Status : Analyzed

Published: 2024-01-05T17:15:08.637

Modified: 2024-01-11T15:57:03.720


Link: CVE-2023-34326

JSON object: View

cve-icon Redhat Information

No data.